By Athanasios Dimoulas, Evgeni Gusev, Paul C. McIntyre, Marc Heyns
This ebook presents a complete monograph on gate stacks in semiconductor know-how. It covers the key most recent advancements and fundamentals and should be invaluable as a reference paintings for researchers, engineers and graduate scholars alike. The reader gets a transparent view of what has been performed to this point, what's the cutting-edge and that are the most demanding situations forward earlier than we come any towards a conceivable Ge and III-V MOS know-how.
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Extra info for Advanced Gate Stacks for High-Mobility Semiconductors (Springer Series in Advanced Microelectronics)
Ezaki, T. Iwamoto, M. Tago, N. Ikarashi, M. Hane, and T. Yamamoto. “Channel direction impact of (110) surface Si substrate on performance improvement in sub-100nm MOSFETs,” in Ext. Abst. SSDM, 2003, pp. 718–719 40 A. Teramoto and T. Ohmi 11. H. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. 5nm Gate Oxide CMOS on (110) Surface-Oriented Si Substrate,” IEEE Trans. Electron Devices, vol. 50, No. 4, 2003, pp. 1001–1008 12. H. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. Toyoshima, “110 GHz cutoﬀ frequency of ultra-thin gate oxide p-MOSFETs on  surface oriented Si substrate,” in VLSI Tech.
In addition, an important concern in any strained Si CMOS technologies including the global and the local ones is strain relaxation, which may come from subsequent processing or from the device geometry. It is, in the simplest case, well known that the strain in strained ﬁlms patterned into isolated areas is relaxed from their edges. Actually, uni-axial strain has been created on biaxial global strain substrates by utilizing this phenomenon [73, 74]. However, any unintentional strain relaxations have to be avoided by carefully designing the process conditions and the device geometry, though the robustness against strain relaxation can be strongly dependent on the strain-application techniques.
Nakamura, and Y. 5nm Gate Oxide CMOS on (110) Surface-Oriented Si Substrate,” IEEE Trans. Electron Devices, vol. 50, No. 4, 2003, pp. 1001–1008 12. H. Momose, T. Ohguro, K. Kojima, S. Nakamura, and Y. Toyoshima, “110 GHz cutoﬀ frequency of ultra-thin gate oxide p-MOSFETs on  surface oriented Si substrate,” in VLSI Tech. , 2002, pp. 156–157, June 2002 13. A. Teramoto, T. Hamada, H. Akahori, K. Nii, T. Suwa, K. Kotani, M. Hirayama, S. Sugawa and T. Ohmi, “Low noise balanced-CMOS on Si(110) surface for analog/digital mixed signal circuits,” IEDM Tech.
Advanced Gate Stacks for High-Mobility Semiconductors (Springer Series in Advanced Microelectronics) by Athanasios Dimoulas, Evgeni Gusev, Paul C. McIntyre, Marc Heyns